An Efficient 32-Bit Online Error Detection & Correction Scheme for Embedded Memory

As technology scales, VLSI performance has experienced an exponential growth. As feature sizes shrink, however, we will face new challenges such as soft errors (single-event upsets) to maintain the reliability of circuits. Recent studies have tried to address soft errors with error detection and correction techniques such as error correcting codes and redundant execution. However, these techniques come at a cost of additional storage or lower performance. Soft errors are a major reliability concern for today’s nanometre technologies. The errors in register files in Application Specific Integrated Circuits (ASIC) can quickly spread to various parts of the system and result in data corruption which may go unnoticed. For example, Single Error Correction (SEC) Hamming code and Triple Modular Redundancy (TMR) provide a high-level mitigation solution for soft errors. We here studied commonly used algorithm in the industry i.e. hamming code which is used to correct one bit error. However, with recent technology soft error correction needs to be more practicable and efficient and keeping in view of that developed a new algorithm. We have successfully designed, synthesized both the algorithm. After comparing various reports we found that our algorithm is more efficient than hamming code algorithm. Simulation results show that the proposed architecture design based on the our developed new algorithm has low area overhead, 93.5% improvement & It is also observed that the power dissipation is low i.e. 98.9% improvement as compared to the hamming code technique approach. Keywords— Error correction code (ECC), Error detection and correction (EDAC), single error correction(SEC) single event correction (SEU), soft error, online, single event upset (SEU).